1. Field of the Invention
The present invention relates to a method for transmitting/receiving serial data in a serial communication system, as well as a serial communication system for the same. More particularly, the present invention relates to a method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same.
2. Description of the Related Art
As generally known in the art, conventional on-chip or off-chip parallel communication systems require a large number of wires, which result in problems including crosstalk between wires, skew, etc. Therefore, off-chip serial communication systems (e.g. Ethernet, USB (Universal Serial Bus), IEEE 1394, PCI-EXPRESS, etc.) are used for wired communication between electric products, Internet communication between computers, communication between functional blocks inside chips, etc. Even in the case of on-chip communication systems, which have adopted only the parallel bus scheme, on-chip serial communication systems are being studied to solve not only the above-mentioned problems of crosstalk between wires and skew, but also the wiring congestion of parallel wires. Such an on-chip serial communication scheme has been adopted for a multifunction, high-performance multicore SoC (System-on-Chip), such as an NoC (Network-on-Chip).
FIG. 1 is a block diagram showing an apparatus for transmitting/receiving serial data according to the prior art.
The conventional serial communication system includes a transmitter 110 for converting input N-bit parallel data 101 into serial data 105 and transmitting it, and a receiver 150 for receiving the serial data from the transmitter 110 and converting it into N-bit parallel data 109.
The transmitter 110 successively converts N-bit parallel data 101, which is stored in a first signal processor 111 of a FIFO (First In First Out) type, into serial data 105 through a serial converter 115, and loads the serial data 105 onto a serial transmission wire 130. The MSB (Most Significant Bit) of the serial data 105 is generally transmitted first.
The receiver 150 converts the successively inputted serial data 105 into parallel data through a parallel converter 151, stores the parallel data in a second signal processor 155, and outputs N-bit parallel data 109.
The first and second signal processors 111 and 155 according to the prior art shown in FIG. 1 may be omitted, and a coder 113 and a decoder 153 may be added if a separate coding scheme is adopted.
Coding schemes applicable to the coder 113 and the decoder 153 shown in FIG. 1 will now be described.
When clocks are extracted from data without separate clock signals, such as in the case of Ethernet (IEEE 802.3), DC-balanced codes (e.g. 8 B/10 B codes) are used. Particularly, according to the DC-balanced coding scheme, transitions are so created in the serial transmission wire 130 that less than five consecutive symbols (0 or 1) should occur. This makes it easier to extract clocks from the serial transmission wire 130.
However, the DC-balanced coding scheme increases the transmitting/receiving power due to the increased number of transitions in the serial transmission wire 130. In addition, 25% overhead occurs because, in order to transmit effective data of 8 bits 10 bits are actually transmitted. The DC-balanced coding scheme is even unnecessary if separate clock signals are used or if the transmitter 110 and the receiver 150 are synchronized as in the case of on-chip communication systems.
There are analog and digital methods for minimizing the transmitting/receiving power when the transmitter 110 and the receiver 150 are synchronized. The analog method includes a low-swing signaling scheme, according to which the signal level is lowered. The digital method includes a scheme (e.g. SILENT coding scheme), according to which the bit transitions on the serial transmission wire 130 are minimized.
The SILENT coding scheme, which has been studied as one of the conventional digital methods, applies XOR (Exclusive OR) codes to the serial transmission scheme, as disclosed in “SILENT: Serialized Low Energy Transition Coding for On-Chip Interconnection Networks”, Kangmin Lee, et al., IEEE ICCAD 2004, pp. 448-451.
FIG. 2 shows a SILENT coding scheme.
The scheme will now be described with reference to FIG. 1 on an assumption that N-bit parallel data is 8-bit data.
The first signal processor 111 shown in FIG. 2 is a buffer of an FIFO type, and transmits successively inputted parallel data W0-W3 to the coder 113. The coder 113 adopts a SILENT coding scheme, which applies XOR codes to a serial transmission scheme, and creates data W′0-W′3 201 that has been coded successively in such a manner that, if a currently transmitted data bit is identical to a previously transmitted data bit, 0 is used, and, if they are different, 1 is used. The serial converter 115 serializes the created data 203, and loads the SILENT-coded serial data 205 onto the serial transmission wire 130 as shown in FIG. 2A.
It is clear from FIG. 2 that, as a result of applying the SILENT coding scheme, there are 6 bit transitions in the SILENT-coded serial data 205 as shown in FIG. 2A, but there are 17 bit transitions in the original serial data 207 to which the SILENT coding has not been applied. The reason the number of bit transitions is reduced by the SILENT coding is that there exists locality between the consecutive parallel data.
However, when such SILENT coding is applied to a serial communication system, the power is reduced efficiently compared with conventional methods applying no coding, while the bit rate has no gain. In other words, even if the SILENT coding is applied to a serial communication system for conversion into serial data, neither the bit rate nor the bandwidth can be increased during serial data transmission.
In addition, serial transmission schemes adopted by serial communication systems employ a small number of transmission wires and, therefore, have a much smaller bandwidth than parallel transmission schemes which employ many transmission wires to transmit a number of bits simultaneously. In an attempt to solve the problem of small transmission bandwidth, the bit rate is increased by a number of times. This results in difficulty in high-speed design, as well as problems related to the area and power resulting from high-speed circuits.
Therefore, there is a need for a scheme capable of increasing the available bandwidth by compressing SILENT-coded data so that the transitions of bits in serial communication systems can be minimized.